Expanded Course Description
- Limits to High Performance
The various impediments to achieving high performance will be detailed.
- Pipelining and High Performance
The usefulness of pipelining as a method for achieving high performance will be presented, as will the inherent limitations. Details on techniques used to overcome these limits will be examined.
- Advanced Memory Design
Advanced techniques for reducing the memory latency problem, such as the use of I/O queues, advanced caching schemes (including multi-level caches), and intelligent memory systems will be examined.
- Special Purpose Processors
The performance benefits and the regimes in which vector processors are most useful will be explored, as well as other specialty chips (such as Digital Signal Processors).
- Single-Chip Processors
The current and future state of supercomputing will be described.
M.D. Hill, N.P. Jouppi, and G. S. Sohi, Readings in Computer Architecture, Morgan Kaufmann Publishers, 2000
Selected papers from the literature
M. Farrens (February 2002)
This course does not have a significant overlap with any other course.